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Agilent HDMP-1685A 1.25 Gbps Four Channel SerDes with 5-pin DDR SSTL_2 Parallel Interface
Data Sheet
Features * 5-bit wide Tx, Rx bus pairs * 208-ball, 23 mm TBGA package * Parallel data I/O and clocks compatible with SSTL_2 (EIA/JESD8-9) * 125 MHz TC, RC clocks * One TC clock for 4 channels * Single or paired RC clocks * LVTTL RefClk input * Source synchronous clocking of transmit data * Source centered clocking of receive data * Double data rate (DDR) parallel transfers * Parallel loopback * Differential BLL serial I/O * Single +3.3 V power supply * Copper drive capability Applications * High density fast ports * Fast serial backplanes * Clusters of computers * Clusters of network units * Link aggregation, trunks The transmitter section's PLL locks to the 125 MHz TC. This clock is then multiplied by 10 to generate the 1250 MHz serial clock for the high-speed serial outputs. The high-speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission.
Functional Description This data sheet describes HDMP1685A, a 1.25 Gbps, four-channel, 5-pin per channel parallel interface SERDES device. The HDMP-1685A 5-pin parallel interface device enables a single ASIC to drive twice as many channels using half as many parallel lines. This is accomplished without increasing the clock frequency by utilizing the bandwidth on the parallel interface more efficiently. The HDMP-1685A SERDES is a single silicon bipolar integrated circuit packaged in a 208-pin BGA. This integrated circuit provides a low-cost, small-form-factor physicallayer solution for multi-link 1.25 Gbps cables or optical transceivers. Each IC contains transmit and receive channel circuitry for all four channels. A 125 MHz LVTTL reference clock must be supplied to the reference clock input pin, RFCT.
The transmitter section accepts four, 5-bit-wide parallel SSTL_2 data (TX [0:3] [0:4]), a 125 MHz SSTL_2 byte clock (TC) and serializes them into four high-speed serial streams. The parallel data is expected to be "8B/10B" encoded data, or equivalent. TX and TC are source synchronous. New data are accepted on both edges of TC; this is called Double Data Rate (DDR). HDMP-1685A finds a sampling window in between the two edges of TC to latch TX [0:3] [0:4] data into the input register of the transmitter section. This timing scheme assumes that the driving ASIC and HDMP-1685A operate in the same clock domain. 8B/10B encoded data comes in 10-bit characters. This data is latched onto the 5 TX pins of each channel in 5-bit groups. It is expected that the beginning half of each 10-bit character is latched on the rising edge of TC.
The receiver section accepts four serial electrical data streams at 1250 MBd and recovers the respective original 10-bit-wide data for each channel over a 5-pin parallel interface. The receiver PLL locks onto the incoming serial signal and recovers the high-speed serial clock and data. The serial data is converted back into 10-bit parallel data, optionally recognizing the 8B/10B comma character to establish byte alignment. If comma character detection is enabled by raising the SYNC signal high, the receiver section is able to detect comma characters and indicate their presence on each channel with the appropriate SYN [0:3] signal(s). The recovered parallel data are presented at SSTL_2-compatible outputs RX [0:3] [0:4], and a pair of 125 MHz SSTL_2 clocks, RC [0:3] [1], and RC [0:3] [0], that are 180 degrees out of phase from one another and which represent the remote clock for that channel. Rising edges of RC [0:3] [1] and RC [0:3] [0] may be used to latch RX data at the destination. Alternatively, both edges of either RC [0:3] [1] or RC [0:3] [0] may be used to latch RX data (DDR). When SYNC is high, the beginning half of the comma character shows up at the rising edge of RC [0:3] [1]. The timing of transmit and receive parallel data with respect to TC and RC [0:3] [0:1] is arranged so that the upstream protocol device can generate and latch data very simply. Specifically, in the TX direction, the ASIC drives four sets of 5-pin TX lines and the TC line with the same timing. The
TC line is similar to a 6th data line that is always toggling to provide timing information to the SERDES. On the RX side, the SERDES drives four sets of 5-pin RX data centered between the edges of RC [0:3] [1] or RC [0:3] [0]. For test purposes, the transceiver provides for on-chip parallel loopback functionality controlled through an input pin. Additionally, the byte-edge alignment feature via detection of the positive comma (K28.5+) character may be disabled. This may be useful in proprietary applications that use alternative methods to align the parallel data. HDMP-1685A Block Diagram The HDMP-1685A (Figure 2) is designed to transmit and receive 10-bit 8B/10B character data over 5-pin-wide parallel busses via high-speed serial communication lines. The parallel data applied to the transmitter is expected to be encoded per the 8B/10B encoding scheme with special reserve characters for link management purposes. Other encoding schemes will also work as long as they provide dc balance and sufficient number of transitions. In order to accomplish this task, the HDMP-1685A incorporates the following: * SSTL_2 Parallel Data I/O * High-Speed Phase Locked Loops * Parallel-to-Serial Converters * High-Speed Serial Clock and Data Recovery Circuitry * Comma Character Recognition Circuitry (K28.5+) * Byte Alignment Circuitry * Serial-to-Parallel Converter
PARALLEL INPUT LATCH For each channel, the transmitter accepts 10-bit characters as two groups of 5-pin single-ended SSTL_2 parallel data at inputs TX [0:3][0:4]. The SSTL_2 TC clock provided by the sender of transmit data is used for all channels as the transmit byte clock. The TX [0:3][0:4] and TC signals must be properly aligned, as shown in Figure 3. TX PLL/CLOCK GENERATOR The transmitter Phase Locked Loop and Clock Generator (TX PLL/CLOCK GENERATOR) block generates all internal clocks needed by the transmitter section to perform its functions. These clocks are based on the transmit byte clock (TC). TC is also used to determine the sampling window for the incoming data latches. Incoming data is synchronous with TC (see Figure 3). FRAME MUX The FRAME MUX accepts the 10-bit-wide parallel data from the INPUT LATCH. Using internally generated high-speed clocks, this parallel data is multiplexed into the 1250 MBd serial data streams. The data bits are transmitted sequentially, from TX [0] to TX [4]. The leftmost bit of K28.5 is on TX [0]. SERIAL OUTPUT SELECT The OUTPUT SELECT block provides a parallel loopback mode for testing purposes. In normal operation, PLUP is set low and the serialized TX [0:3] [0:4] data are placed at SO [0:3] +/-.
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When parallel wrap-mode is activated by setting PLUP high, the SO [0:3]+/- pins are held static at logic 1 and the serial output signal reflecting TX [0:3] [0:4] data is internally wrapped to the INPUT SELECT block of the receiver section. SERIAL INPUT SELECT The INPUT SELECT block determines whether the signal at SI [0:3]+/- or the internal loopback serial signal is used to drive RX [0:3] [0:4]. In normal operation, PLUP is set low and the serial data is accepted at SI [0:3]+/-. When PLUP is set high, the outgoing high-speed serial signal is internally looped back from the transmitter section to the receiver section. This feature allows parallel loopback testing, exclusive of the transmission medium. RX PLL/CLOCK RECOVERY The RX PLL/CLOCK RECOVERY block is responsible for frequency and phase locking onto the incoming serial data stream and recovering the bit and byte clocks. It does this by continually frequency locking onto the 125 MHz reference clock, and then phase locking onto the selected input data stream. An internal signal detection circuit monitors the presence of the input, and invokes the phase detection once the minimum differential input signal level is supplied (AC Electrical Specifications). Once bit locked, the receiver generates the high-speed sampling clock at 1250 MHz for the input sampler.
SERIAL INPUT SAMPLER The INPUT SAMPLER converts the serial input signal into a retimed bit stream. In order to accomplish this, it uses the highspeed serial clock recovered from the RX PLL/CLOCK RECOVERY block. This serial bit stream is sent to the FRAME DEMUX AND BYTE SYNC block. FRAME DEMUX, BYTE SYNC The FRAME DEMUX AND BYTE SYNC block is responsible for restoring the 10-bit character from the high-speed serial bit stream. This block is also responsible for recognizing the comma character (K28.5+) of positive disparity (0011111xxx). When recognized, the FRAME DEMUX AND BYTE SYNC block works with the RX PLL/CLOCK RECOVERY block to properly select the parallel data edge out of the bit stream so that the comma character starts at RX[0:3][0]. When a comma character is detected and realignment of the receiver byte clock RC[0:3][0:1] is necessary, this clock is stretched, not slivered, to the next possible correct alignment position. This clock will be fully aligned by the start of the second 2-byte or 4-byte ordered set. The second comma character received will be aligned with the rising edge of RC[0:3][1]. Comma characters of positive disparity must not be transmitted in consecutive bytes to allow the receiver byte clocks to maintain their proper recovered frequencies.
PARALLEL OUTPUT DRIVERS The OUTPUT DRIVERS present the recovered 10-bit character in two groups onto the 5-pin RX bus, properly aligned to the receive byte clock RC [0:3] [0:1] as shown in Figure 5. These output data buffers provide single-ended SSTL_2 compatible signals. Unlike the TX, where all four channels are driven with the same transmit byte clock (TC), each receive channel provides its own clock aligned with its own data, so the recovered clocks may not be phase aligned. SSTL_2 COMPATIBILITY HDMP-1685A works with protocol devices whose VDDQ voltage is nominally set at 2.5 Volts. RX [0:3][0:4], RC [0:3][0:1] pins generate output voltages that are compatible with the SSTL_2 standard (EIA/JESD8-9). In addition, these devices provide a VREFR output pin allowing the receiving device to differentially detect a high or a low. The devices receive inputs on their TX [0:3][0:4] and TC pins that are also SSTL_2 compatible. The VREFT input pin is driven by a voltage divider whose supply voltage is at the same level as the VDDQ supply of the protocol device. This allows differential detection of a high or a low at TX parallel inputs.
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RFCT
4-CHANNEL ASIC
RC01/0
RC11/0
RC21/0
RC31/0 SI3
RX0
RX1
RX2
HDMP-1685A
SO0
SO1
SO2
Figure 1. Typical application of the four channel SERDES.
INPUT LATCH
TX(0:3)[0:4]
FRAME MUX
OUTPUT SELECT
SO3
SI0
SI1
SI2
RX3
TX0
TX1
TX2
TX3
TC
SO[0:3]
PLUP TC TX PLL CLOCK GENERATOR TX CLOCKS INPUT SELECT Sl[0:3]
CAP0 CAP1 RFCT RC(0:3)[0:1] SYNC SYN(0:3)
RX PLL CLOCK RECOVERY
OUTPUT DRIVER
RX(0:3)[0:4]
FRAME DEMUX AND BYTE SYNC
RX CLOCKS
INPUT SAMPLER
Figure 2. Block diagram of HDMP-1685A.
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HDMP-1685A Timing Characteristics - Transmitter Sections TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V Symbol tTXCT[2] tTXCV[2] t_txlat[1] Parameter TX [0:3][0:4] Input Data and TC Clock Transition Range TX [0:3][0:4] Input Data and TC Clock Valid Time Transmitter Latency Units ps ps ns bits 2400 4 5 Min. Typ. Max. 1600
Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the leading edge of the first half of a parallel 10-bit word and the leading edge of the first transmitted serial output bit of that 10-bit word. 2. Agilent`s HDMP-1685A internally generates another clock which is 90 degrees out of phase with the TC clock supplied. This clock, which will have its edges at the center of the data valid eye, is used to clock in the TX[0:4] data. Setup and hold times are taken care of by the HDMP-1685A provided the specifications indicated are met.
8 ns TXCT TX[0:3][0:4]
TXCV
TXCV
TC
Figure 3. Transmitter section parallel input timing.
10-BIT CHAR A
10-BIT CHAR B
SO[0:3]
TX[0] TXLAT
TX[9]
TX[0:3][0:4]
CHAR B[4:0]
CHAR B[9:5]
TC
Figure 4. Transmitter section latency. TX[0] is first on serial wire.
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HDMP-1685A Timing Characteristics - Receiver Sections - Rising Edge Clocking TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol f_lock B_sync[1,2] tRXS tRXH Parameter Frequency Lock at Powerup Bit Sync Time RX [0:3][0:4] Setup Time (Data Valid Before Clock) RX [0:3][0:4] Hold Time (Data Valid After Clock) RC [0:3][1] to RC [0:3][0] Skew RC [0:3][1] and RC [0:3][0] Duty Cycle t_rxlat[3] Receiver Latency Units s bits ps ps ns % ns bits 1200 800 3.5 40 16 20 4.5 60 Min. Typ. Max. 500 2500
Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. 2. Tested using CPLL = 0.1 F. 3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC [0:1]).
8 ns
RC[0:3][1]
RC[0:3][0]
RXS RXH
RXS RXH
RX[0:3][0:4]
Figure 5a. Receiver section parallel output timing using rising edge of both RC[0:3][0] and RC[0:3][1].
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HDMP-1685A Timing Characteristics - Receiver Sections - Rising and Falling Edge Clocking TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V Symbol f_lock B_sync[1,2] tRXS tRXH t_rxlat[3] Parameter Frequency Lock at Powerup Bit Sync Time RX [0:3][0:4] Setup Time (Data Valid Before Clock) RX [0:3][0:4] Hold Time (Data Valid After Clock) RC [0:3][1] and RC [0:3][0] Duty Cycle Receiver Latency Units s bits ps ps % ns bits 1000 800 40 16 20 60 Min. Typ. Max. 500 2500
Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. 2. Tested using CPLL = 0.1 F. 3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC [0:1]).
8 ns
RC[0:3][0] or RC[0:3][1]
RXS RXH
RXS RXH
RX[0:3][0:4]
Figure 5b. Receiver section parallel output timing using rising and falling edge of either RC[0:3][0] or RC[0:3][1].
10-BIT CHAR B
10-BIT CHAR C
SI[0:3] RX[0] RXLAT RX[9]
RX[0:3][0:4]
CHAR A[4:0]
CHAR A[9:5]
CHAR B[4:0]
RC[0:3][1]
RC[0:3][0]
Figure 6. Receiver section latency. First bit on serial wire drives RX[0:3][0].
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HDMP-1685A Absolute Maximum Ratings TA = 25C, except as specified. Sustained operation at or beyond any of these conditions may result in long-term reliability degradation or permanent damage, and is not recommended. Symbol VCC VIN,LVTTL VIN,SSTL VIN,HS_IN Tstg Tj TC Parameter Supply Voltage RFCT LVTTL Input Voltage SSTL Input Voltage HS_IN Input Voltage (Differential) Storage Temperature Junction Temperature Case Temperature Units V V V V C C C -65 0 0 Min. -0.5 -0.7 -0.7 Max. 5.0 VCC + 2.8 VCC + 0.7 2.2 +150 +125 95
HDMP-1685A Guaranteed Operating Rates TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Parallel Clock Rate (MHz) Min. Max. 124.0 126.0 Serial Baud Rate (MBaud) Min. Max. 1240 1260
HDMP-1685A Reference Clock and Transmit Byte Clock Requirements TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol f Ftol SymmRFC SymmTC Parameter Nominal Frequency Frequency Tolerance Symmetry (Duty Cycle) Reference Clock Symmetry (Duty Cycle) Transmit Byte Clock Units MHz ppm % % -100 40 40 Min. Typ. 125 +100 60 60 Max.
HDMP-1685A LVTTL I/O DC Electrical Specifications TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol VIH,LVTTL VIL,LVTTL VOH,LVTTL VOL,LVTTL IIH,LVTTL IIL,LVTTL Parameter LVTTL Input High Voltage Level, Guaranteed High Signal for All Inputs LVTTL Input Low Voltage Level, Guaranteed Low Signal for All Inputs LVTTL Output High Voltage Level, IOH = -400 A LVTTL Output Low Voltage Level, IOL = 1 mA Input High Current, VIN = 2.4 V, VCC = 3.45 V Input Low Current, VIN = 0.4 V, VCC = 3.45 V Units V V V V A A Min. 2 0 2.2 0 Typ. Max. 5.5 0.8 VCC 0.5 40 -600
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HDMP-1685A SSTL_2 I/O DC Electrical Parameters TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V, VDDQ = 2.30 V to 2.70 V. VDDQ is the FC-1/MAC device I/O supply voltage. SSTL-2 inputs can receive LVTTL signals successfully. SSTL-2 outputs do not output LVTTL compliant levels. Symbol VREFT VIH VIL VREFR VOH VOL Parameter SSTL_2 Input Reference Voltage Input High Voltage Input Low Voltage SSTL_2 Output Reference Voltage Output High Voltage Output Low Voltage Units V V V V V V Min. 1.15 VREFT +0.18 -0.30 1.15 VREFR +0.38 GND 1.25 Typ. 1.25 Max. 1.35 VDDQ +0.30 VREFT -0.18 1.35 VDDQ VREFR -0.38
HDMP-1685A AC Electrical Specifications (TRx) TA = 0C to T C = 85C, VCC = 3.15 V to 3.45 V Symbol tr,RFCT tf,RFCT tr,SSTLo tf,SSTLo trs, HS_OUT tfs, HS_OUT trd, HS_OUT tfd, HS_OUT VIP,HS_IN VOP,HS_OUT [1] Parameter RFCT LVTTL Input Rise Time, 0.8 to 2.0 Volts RFCT LVTTL Input Fall Time, 2.0 to 0.8 Volts SSTL Output Rise Time, 1.0 V to 1.6 V SSTL Output Fall Time, 1.6 V to 1.0 V HS_OUT Single-Ended (SO[0:3]) Fall Time (20% - 80%) HS_OUT Differential Rise Time HS_OUT Differential Fall Time Units ns ns ns ns 85 85 85 85 200 1000 1200 1300 ps ps ps Min. 0 0 0.4 0.28 205 180 Typ. Max. 2.4 2.4 1.5 1.5 300 300 300 300 2000 1800
HS_OUT Single-Ended (SO[0:3]) Rise Time (20% - 80%) ps
HS_IN (SI[0:3]) Input Peak-To-Peak Differential Voltage mV HS_OUT Output Pk-Pk Diff. Voltage (Z0=50 Ohms, Fig.10) mV
Note: 1. Output Peak-to-Peak Differential Voltage specified as SO[0:3]+ minus SO[0:3]-. The amplitude will be 25% higher when terminating into 75 loads.
WAVEFORM MATH f1 = 3 - 4 f2 = 1 - 2 FUNCTION f1 f2
X1
X2
DEFINE FUNCTION... DISPLAY off on
VERTICAL SCALE auto 120.0 ps/div Y 1 (f2) = -637.00 mV 2 (f2) = 636.00 mV = 130.3664 ns X 250 mV/div Y OFFSET 0.0 V 130.549 ns 131.349 ns 800 ps 1.27300 V 1/X = 1.250 GHz manual
Y SCALE
Figure 7. Eye diagram of a high speed differential output.
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HDMP-1685A Output Jitter Characteristics - Transmitter Section TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol RJ[1] DJ[1] Parameter Random Jitter at DOUT, the High Speed Electrical Data Port, specified as 1 sigma deviation of the 50% crossing point (RMS) Deterministic Jitter at DOUT, the High Speed Electrical Data Port (pk-pk) Units ps ps Typ. 11 26
Note: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement method shown in Figure 8.
A 70311A CLOCK SOURCE
A 70841B PATTERN GENERATOR +K28.5, -K28.5
A 70841 PATTERN GENERATOR 1000001111 + DATA - DATA 125 MHz
A 83480A OSCILLOSCOPE TRIGGER CH1 CH2
1.25 GHz
+ DATA - DATA A 83480A OSCILLOSCOPE
DIVIDE BY 10 CIRCUIT
DIVIDE BY 2
TRIGGER CH1 CH2
A 70311A CLOCK SOURCE SOi+ BIAS TEE TC TXi[0:4] SOi-
HDMP-1685 PLUP
VARIABLE DELAY
SOi+
SOi-
SIi- SIi+ SYNC PLUP
HDMP-1685A HDMP-1685
125 MHz TC TXi[0:4]
RXi[0:4]
1.4 V
0011111000 (STATIC K28.7)
A. BLOCK DIAGRAM OF RJ MEASUREMENT METHOD
B. BLOCK DIAGRAM OF DJ MEASUREMENT METHOD
Figure 8. Transmitter jitter measurement method.
HDMP-1685A Thermal and Power Temperature Characteristics (TRx) TA = 0C to TC = 85C, VCC = 3.15 V to 3.45 V Symbol ICC,TRx PD, TRx [1] jc[1] Tj TC Parameter Transceiver VCC Supply Current, TA = 25C Transceiver Power Dissipation, Outputs Connected per Recommended Bias Terminations with 27-1 PRBS Pattern Thermal Resistance, Junction to Case Junction Temperature (absolute maximum) Case Temperature (absolute maximum) Units mA W C/W C C Typ. 900 2.97 7.8 0 0 +125 +95 3.5 Max.
Note: 1. Based on independent package testing by Agilent. ja for these devices is 36C/W for the HDMP-1685A. ja is measured on a standard 3x3" FR4 PCB in a still air environment. To determine the actual junction temperature in a given application, use the following: Tj = Tc + (jc x PD), where Tc is the case temperature measured on the top center of the package and PD is the power being dissipated.
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HDMP-1685A I/O Type Definitions I/O Type I-LVTTL I-SSTL2 O-SSTL2 HS_OUT HS_IN C S Definition Input LVTTL, floats high when left open Input SSTL_2, floats low when left open Output SSTL_2 50 matched Output Driver. Will drive AC coupled 50 loads. PECL level compatible (Figure 10). PECL level compatible. Must be AC coupled (Figure 10). External Circuit Node Power Supply or Ground
HDMP-1685A Pin Input Capacitance (TRx) Symbol CINPUT Parameter Input Capacitance on SSTL input pins Units pF Typ. 1.6 Max.
I_TTL
VCC
VCC
VBB 1.4 V
GND ESD PROTECTION GND
Figure 9. LVTTL input simplified circuit schematic (for RFCT).
HS_OUT
VCCP Zo Zo VCC VCC
HS_IN
+ - VCC
+ -
SO[0:3]+ 0.01 F
Zo = 50 2 * Zo = 100
SI[0:3]+
SO[0:3]- 0.01 F GND ESD
PROTECTION
Zo = 50 SI[0:3]- GND ESD
PROTECTION
GND
GND
NOTES: 1. HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. 2. CAPACITORS MAY BE PLACED AT THE SENDING END OR THE RECEIVING END.
Figure 10. HS_OUT and HS_IN simplified circuit schematic.
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VCC (SERDES) = 3.3 V
VCC (SERDES) = 3.3 V R1 VDDQ (MAC)
VCC (MAC)
VCC 0.1 F VREFR R2
VCC VDDQ VREFT
RX[0:3][0:4] RC[0:3][0:1]
RS = 50 UNTERMINATED
DATAIN
TX[0:3][0:4] TC
RS = 50 USE TERMINATION, IF NECESSARY, TO DELIVER PROPER VOLTAGE SWINGS AT TX[0:4] VDDQ (MAC) R1
DATAOUT
VREFT 0.1 F R2 HDMP-1685 MAC
NOTE: VREFR ON EACH DEVICE MAY BE USED TO DRIVE VREFT ON THE OTHER DEVICE INSTEAD OF USING THE CONFIGURATION ABOVE. VREFR SHOULD BE BYPASSED WITH 0.1 F IN THIS CASE. IF USED, R1 AND R2 SHOULD BE 500-1000 . 1% RESISTORS SHOULD BE USED FOR R1 AND R2. WHEN USING THE CONFIGURATION ABOVE, VREFT TO THE MAC SHOULD BE SET TO 1.25 V NOMINAL. USING THIS VALUE CENTERS VREFR RELATIVE TO THE RX[0:3][0:4] OUTPUT SWINGS PROVIDED BY THE HDMP-1685A.
Figure 11. O-SSTL_2 and I-SSTL_2 simplified circuit schematic.
01 A B C D E F G H J K L M N P R T U TX04 TX14 RX04 GND
02 VCC
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
GND SYN1 RC10 RX10 RX14 GND RC11 RX11 VCR1 VCR0 VCR1 RX12 GND
VCR1 VCC
GND RX21 VCR2
GND VCR2 GND SYN3 RC30 RC31 VCC VCR3 GND RX30 RX31 RX32 RX33 RX34 VCR3 GND GND
GND SYN2 RX20 RX22 RC20 VCR2 RX23 RC21 GND RX24
RX00 RX01 VCR0 GND GND RX13 VRFR RC00 RC01 RX02 RX03 SYN0 VCR0 GND GND VCC GND GNDA VCCP VCC VCCA VCR
TX22 TX21 TX20 VCR3 TX24 TX23 VCC GND GND VCC TC
TX10 TX11 TX12 TX13 GND GND GND VCC
TX33 TX32 TX31 TX30 TX34 PLUP VCC
TX00 TX01 TX02 TX03 VRFT RFCT GND GND VCC GND SO0-- GND SO1-- GND CAP0 GND SO2+ GND SO3+
VCC SO0+ GND SO1+ GNDA CAP1 GND SO2-- GND SO3-- VCC VCC VCP0 GND VCP1 GND VCCA GND VCP2 GND VCP3 VCC VCC
GND
VCC SYNC
GND GND
GND GND SIO-- SI0+
SI1-- SI1+ GND GND SI2-- SI2+ GND SI3-- SI3+ GND GND GND
Figure 12. Pinout of HDMP-1685A (top view).
12
VCC
+ 10 F *
Filtering Schematic
A10 B7 A2 A9 0.1 F
0.1 F A13 A16
0.1 F
VCC
VCR VCC
VCR
VCR VCR
C4 0.1 F C5 D3 F3 G4
VCR VCR VCR VCR VCC
VCR VCC VCR VCR
C11 C14 C15 E14 G17 J14 K16
0.1 F
L4 0.1 F
HDMP-1685A GUIDELINES FOR DECOUPLING CAPACITOR PLACEMENTS/CONNECTIONS
VCR VCC VCC
0.1 F
VCC VCC N15
0.1 F
0.1 F R4 VCC VCCA VCC R16
VCP VCC
VCP
VCP
VCP T13
VCC VCC
VCC 11
T3 T4
T5
U5
T7
T9
T11
0.1 F
0.1 F
VCC 0.1 F +
1 H 10 F 10 F + + 0.1 F
*
+ OPTIONAL - PROVIDES INCREASED LOW FREQUENCY DECOUPLING.
01 0.1 F A B C D E F G H J GND
02
03
04
05
06
07
08
09
10 10 F*
T14 R14 0.1 F PLACEMENT NOT CRITICAL. INDICATES THE NEED FOR ADDITIONAL LOW FREQUENCY CAPACITIVE DECOUPLING. 12
VCC
13
14
15 0.1 F
16
17
0.1 F VCC GND GND VCR VCR GND VCR GND 0.1 F VCR GND GND VCC VCR GND VCR GND
VCC
GND
VCR
GND
VCR
GND
VCR GND
VCC
VCR
GND
VCR 0.1 F VCC 0.1 F
GND GND VCR 0.1 F
* 10 F PLACEMENT NOT CRITICAL - INDICATES NEED FOR LOW-FREQUENCY BYPASS CAPACITANCE
K L M N P R T U GND GND GND
GND GND
GND VCC 0.1 F GND GND GND VCP VCC 0.1 F GND VCP GND GND GND GND VCP GND GND GND GND 0.1 F
GND
GND
HDMP-1685A
VCC
VCC 0.1 F
GND VCC
VCC VCC
VCC VCP VCC
GND GND GND
VCC GND GND GND
GND VCCA GND GND GND 0.1 F 10 F
0.1 F
TO VCCA PI-FILTER (SEE SCHEMATIC)
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HDMP-1685A TRx I/O Definition Name CAP0 CAP1 PLUP Pin P09 R09 N14 I-SSTL2 Parallel Loopback Enable Input: When set high, a high-speed serial signal from the transmitter section's serial output select block, reflecting TX data, is driven to the receiver section's serial input select block. RX data reflects this serial signal. Also when in parallel loopback mode, the SO [0:3]+/- outputs are held static at logic 1. LVTTL Reference Clock: RFCT is a 125 MHz clock signal supplied to the IC. Receiver Byte Clocks: The receiver sections drive 125 MHz receive byte clocks RC [0:3] [0:1]. Type C Signal Loop Filter Capacitor: A loop filter capacitor for the internal PLLs must be connected across the CAP0 and CAP1 pins. (typical value = 0.1 F)
RFCT RC00 RC01 RC10 RC11 RC20 RC21 RC30 RC31 RX00 RX01 RX02 RX03 RX04 RX10 RX11 RX12 RX13 RX14 RX20 RX21 RX22 RX23 RX24 RX30 RX31 RX32 RX33 RX34 SI0+ SI0SI1+ SI1SI2+ SI2SI3+ SI3-
R01 E01 E02 A05 B05 C10 D10 B16 B17 D01 D02 E03 E04 C01 A06 B06 C06 D06 A07 B11 A12 B12 C12 D12 C17 D14 D15 D16 D17 U04 U03 U07 U06 U11 U10 U14 U13
I-LVTTL O-SSTL2
O-SSTL2
Data Outputs: Four 5-pin data busses. RX [0:3] [0] are the first bits received.
HS_IN
Serial Data Inputs: High-speed inputs. Serial data are accepted from the SI [0:3]+/inputs except when PLUP is high.
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HDMP-1685A TRx I/O Definition, continued Name SO0+ SO0SO1+ SO1SO2+ SO2SO3+ SO3SYNC Pin R05 P05 R07 P07 P11 R11 P13 R13 R17 Type HS_ OUT Signal Serial Data Outputs: High-speed outputs. These lines are active except when PLUP is high, in which case these outputs are held static at logic 1.
I-SSTL2
Enable Byte Sync Input: When high, turns on the internal byte sync functions to allow clock synchronization to a comma character of positive disparity (0011111XXX). When the line is low, the function is disabled and will not reset registers and clocks, or strobe the SYN [0:3] lines. Byte Sync Outputs: Active high outputs. Used to indicate detection of a comma character of positive disparity (0011111XXX) when SYNC is enabled.
SYN0 SYN1 SYN2 SYN3 TC TX00 TX01 TX02 TX03 TX04 TX10 TX11 TX12 TX13 TX14 TX20 TX21 TX22 TX23 TX24 TX30 TX31 TX32 TX33 TX34 VREFT VREFR
F02 A04 B10 B15 K17 N01 N02 N03 N04 M01 J01 J02 J03 J04 H01 G16 G15 G14 H17 H16 L17 L16 L15 L14 M17 P01 D07
O-SSTL2
I-SSTL2 I-SSTL2
Transmit Byte Clock: This signal is used to latch transmit data for all channels into the IC. Data Inputs: Four 5-pin data busses. TX [0:3] [0] are the first bits transmitted.
I-S O-S
TX Parallel Interface SSTL_2 Reference Voltage: Voltage reference derived from 2 resistor network with VDDQ (ASIC) as supply, as recommended in Figure 11. RX Parallel Interface SSTL_2 Reference Voltage: Provided by HDMP-1685A. Drives the VREF input of the ASIC.
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HDMP-1685A TRx I/O Definition, continued Name VCC Pin A02 A10 C14 G04 J14 K16 L04 N15 R04 R14 R16 T03 T04 T14 U05 T09 C04 D03 F03 A09 B07 C05 A13 A16 C11 C15 E14 G17 T05 T07 T11 T13 R08 Type S Signal Power Supply: Normally 3.3 volts. Used for logic, SSTL inputs, and LVTTL I/O.
VCCA VCR0
S S
Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the PLLs and high-speed analog cells. Rx SSTL2 Output Power Supply: Normally 3.3 volts. Used for all SSTL2 receiver output buffer cells.
VCR1
VCR2
VCR3
VCP0 VCP1 VCP2 VCP3 GNDA
S
High-Speed Output Supply: Normally 3.3 volts. Used only for the last stage of the high-speed transmitter output cells (HS_OUT) as shown in Figure 10. Due to high current transitions, this VCC should be well bypassed to a ground plane. Analog Ground: Normally 0 volts. All GND pads on the chip are connected to one ground slug in the package, which then distributes these to GND balls.
S
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HDMP-1685A TRx I/O Definition, continued Name GND Pin A01 A03 A11 A15 A17 B04 B09 C07 C16 D04 D05 D11 E15 F04 F17 G03 K03 K04 K14 K15 L03 P04 P06 P08 P10 P12 R03 R06 R10 R12 R15 T02 T06 T08 T10 T12 T15 T16 U01 U02 U08 U09 U12 U15 U16 U17 Type S Signal Logic Ground: Normally 0 volts. All GND pads on the chip are connected to one ground slug in the package, which then distributes these to GND balls.
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HDMP-1685A TRx I/O Definition, continued Name NC Pin A08 A14 B01 B02 B03 B08 B13 B14 C02 C03 C08 C09 C13 D08 D09 D13 E16 E17 F01 F14 F15 F16 G01 G02 H02 H03 H04 H14 H15 J15 J16 J17 K01 K02 L01 L02 M02 M03 M04 M14 M15 M16 N16 N17 P02 P03 P14 P15 P16 P17 R02 T01 T17 Type Signal These pins are connected to an isolated pad and have no functionality. They may be left open, or LVTTL levels may be applied.
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Package Drawing
D1 S e O (4x)
A2 A
e
S
E1
E D C B A 12345 Nx0b eee M Z X Y [-Z-] SEATING PLANE (CAVITY DOWN) (BACKFILL) DETAIL A ddd Z
A1 CORNER [-Y-]
D
[-X-]
[-Z-] SEATING PLANE
A3
A1
(BACKFILL) DETAIL A E DIMENSIONS IN MILLIMETERS SYMBOL MIN. NOM. A A1 A2 A3 D D1 E E1 MD/ME N TOLERANCE OF FORM AND POSITION SYMBOL ddd eee MIN. NOM. MAX. 0.15 0.30 N1 O b e 0.60 0.60 0.75 1.27 0.10 0.90 1.35 0.60 0.85 0.15 23.00 0.20 20.32 BSC 23.00 0.20 20.32 BSC 17 208 4 1.50 0.65 0.90 MAX. 1.65 0.70 0.95
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www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. May 7, 2001 Obsoletes 5988-1304EN 5988-2143EN

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